Intel Xeon “Sapphire Rapids” Memory Detailed, Resembles AMD 1st Gen EPYC: Decentralized 8-Channel

Intel Xeon “Sapphire Rapids” Memory Detailed, Resembles AMD 1st Gen EPYC: Decentralized 8-Channel

Intel’s upcoming Xeon “Sapphire Rapids” processor functions a memory interface topology that carefully resembles that of very first-era AMD EPYC “Rome,” thanks to the multi-chip module layout of the processor. Back in 2017, Intel’s competing “Skylake-SP” Xeon processors were being centered on monolithic dies. Regardless of being unfold across many memory controller tiles, the 6-channel DDR4 memory interface was depicted by Intel as an edge about EPYC “Rome.” AMD’s 1st “Zen” centered company processor was a multi-chip module of 4 14 nm, eight-main “Zeppelin” dies, just about every with a 2-channel DDR4 memory interface that extra up to the processor’s 8-channel I/O. A great deal like “Sapphire Rapids,” a CPU core from any of the four dies experienced access to memory and I/O controlled by any other die, as the 4 ended up networked in excess of the Infinity Fabric interconnect in a configuration that basically resembled “4P on a stick.”

With “Sapphire Rapids,” Intel is using a largely related approach—it has 4 compute tiles (dies) as a substitute of a monolithic die, which Intel claims helps with scalability in both equally directions and every single of the 4 compute tiles has a 2-channel DDR5 or 1024-bit HBM memory interface, which increase up to the processor’s 8-channel DDR5 total I/O. Intel states that CPU cores from each and every tile has equivalent accessibility to memory, final-stage cache, and I/O managed by yet another die. Inter-tile conversation is dealt with by EMIB actual physical media (fifty five micron bump-pitch wiring). UPI 2. will make up the inter-socket interconnect. Every of the 4 compute tiles has 24 UPI two. back links that function at 16 GT/s. Intel didn’t detail how memory is offered to the functioning technique, or the NUMA hierarchy, on the other hand substantially of Intel’s engineering work appears to be centered on building this disjointed memory I/O work as if “Sapphire Rapids” have been a monolithic die. The enterprise promises “dependable minimal-latency, large cross-sectional bandwidth throughout the SoC.”

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