(PR) Rambus Innovates 8.4 Gbps HBM3-ready Memory Subsystem

Rambus Inc., a premier chip and silicon IP supplier generating information more rapidly and safer, today introduced the Rambus HBM3-all set memory interface subsystem consisting of a fully-integrated PHY and electronic controller. Supporting breakthrough knowledge fees of up to 8.4 Gbps, the solution can produce about a terabyte for each 2nd of bandwidth, more than double that of higher-close HBM2E memory subsystems. With a market place-main posture in HBM2/2E memory interface deployments, Rambus is preferably suited to enable customers’ implementations of accelerators using following-generation HBM3 memory.

“The memory bandwidth specifications of AI/ML training are insatiable with major-edge schooling models now surpassing billions of parameters,” claimed Soo Kyoum Kim, associate vice president, Memory Semiconductors at IDC. “The Rambus HBM3-all set memory subsystem raises the bar for effectiveness enabling point out-of-the-artwork AI/ML and HPC purposes.”

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